by Bharat S. Rawal, Kumar Krishnamani, John Maxwell. AVX Corporation
With and increase use of multilayer ceramic capacitors (MLC’s) in surface mount technology (SMT) the understanding of the mechanical properties and thermal stress resistance parameters MLCs is essential for zero defect soldering and sub ppm failure rates. In this paper, various aspects of SMT including zero defect design, placement considerations, thermal stress resistance parameters and post solder handling are reviewed. Special emphasis is given to parameters responsible for thermal shock behavior of the MLCs with review of the effect of overall component thickness, tempature gradients and termination of MLC’s.